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CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
Integrated Device Technology, Inc.
IDT723622 IDT723632 IDT723642
FEATURES:
* Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) * Two independent clocked FIFOs buffering data in opposite directions * Memory storage capacity: IDT723622-256 x 36 x 2 IDT723632-512 x 36 x 2 IDT723642-1024 x 36 x 2 * Mailbox bypass register for each FIFO * Programmable Almost-Full and Almost-Empty flags * Microprocessor Interface Control Logic * IRA, ORA, AEA, and AFA flags synchronized by CLKA * IRB, ORB, AEB, and AFB flags synchronized by CLKB * Supports clock frequencies up to 67MHz
* Fast access times of 11ns * Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving 120-pin Thin Quad Flatpack (PF) * Low-power 0.8-Micron Advanced CMOS technology * Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT723622/723632/723642 is a monolithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memory which supports clock frequencies up to 67MHz and have read access times as fast as 11ns. Two independent 256/512/ 1024x36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programable flags (almost
FUNCTIONAL BLOCK DIAGRAM
CLKA
MBF1 Mail 1 Register 256 x 36 512 x 36 1024 x 36 SRAM
Input Register
Output Register
W/RA ENA MBA
CSA
Port-A Control Logic
RST1
FIFO1, Mail1 Reset Logic
36
36
Write Pointer
Read Pointer Status Flag Logic ORB
AFA
FS0 FS1 A0 - A35
IRA
FIFO 1
AEB
Programmable Flag Offset Registers
9 FIFO 2
B0 - B35
ORA
AEA
36
Status Flag Logic Write Pointer
36
IRB
AFB
FIFO2, Mail2 Reset Logic
Read Pointer
RST2
Output Register
256 x 36 512 x 36 1024 x 36 SRAM Mail 2 Register
Input Register
Port-B Control Logic
CLKB
CSB W/RB
ENB MBB
MBF2
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
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COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-3022/3
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
Full and almost Empty) to indicate when a selected number of words is stored in memory. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices may be used in parallel to create wider data paths. The IDT723622/723632/723642 is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-toHIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be
asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The Input Ready (IRA, IRB) and Almost-Full (AFA, AFB) flags of a FIFO are two-stage synchronized to the port clock that writes data into its array. The Output Ready (ORA, ORB) and Almost-Empty (AEA, AEB) flags of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the Almost-Full and Almost-Empty flags of both FIFOs can be programmed from Port A. The IDT723622/723632/723642 is characterized for operation from 0C to 70C.
PIN CONFIGURATION
NC NC VCC CLKB ENB
MBF1
W/RB CSB
MBF2 AEA AFA
RST1
FS1 GND FS0
NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
VCC ORA IRA
CSA
VCC
W/RA ENA CLKA GND NC
RST2
GND IRB ORB
MBB
MBA
AFB AEB
PQ132-1
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC
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PQF Package TOP VIEW NOTES: 1. NC - no internal connection 2. Uses Yamaichi socket IC51-1324-828
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND CLKA ENA W/RA
RST2 MBB MBF1
FS0 GND FS1
IRA ORA VCC
CSA
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
VCC
ENB CLKB VCC
AFA AEA MBF2 MBA RST1
CSB W/RB
ORB IRB GND
AEB AFB
A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
PN120-1
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND
GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC B7 B8 B9 B10 B11
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
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TQFP TOP VIEW
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol A0-A35 Name Port-A Data Port-A Almost -Empty Flag Port-B Almost -Empty Flag Port-A Almost -Full Flag Port-B Almost -Full Flag Port-B Data Port-A Clock I/O I/0 O (Port A) O (Port B) O (Port A) O (Port B) I/O I Description 36-bit bidirectional data port for side A. Programmable almost-empty flag synchronized to CLKA. It is LOW when the number of words in FIF02 is less than or equal to the value in the almost-empty A offset register, X2. Programmable almost-empty flag synchronzed to CLKB. It is LOW when the number of words in FIF01 is less than or equal to the value in the almost-empty B offset register, X1. Programmable almost-full flag synchronized to CLKA. It is LOW when the number of empty locations in FIF01 is less than or equal to the value in the almost-full A offset register, Y1. Programmable almost-full flag synchronized to CLKB. It is LOW when the number of empty locations in FIF02 is less than or equal to the value in the almost-full B offset register, Y2. 36-bit bidirectional data port for side B. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the LOW-to-HIGH transition of CLKB.
AEA AEB AFA AFB
B0 - B35 CLKA
CLKB
Port-B Clock
I
CSA CSB
ENA ENB FS1, FS0
Port-A Chip Select Port-B Chip Select Port-A Enable Port-B Enable Flag Offset Selects
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on port A. The AO-A35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The BO- B35 outputs are in the high-impedance state when CSB is HIGH.
I
I I I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The LOW-to-HIGH transition of a FlFO's reset input latches the values of FSO and FS1. If either FSO or FS1 is HIGH when a reset input goes HIGH, one of the three preset values is selected as the offset for the FlFOs almost-full and almost-empty flags. If both FIFOs are reset simultaneously and both FSO and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 almost empty offsets for both FlFOs. IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is LOW, FIFO1 is full and writes to its array are disabled. IRA is set LOW when FIFO1 is reset and is set HIGH on the second LOW-to-HIGH transition of CLKA after reset. IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is LOW, FIFO2 is full and writes to its array are disabled. IRB is set LOW when FIFO2 is reset and is set HIGH on the second LOW-to-HIGH transition of CLKB after reset. A HIGH level on MBA chooses a mailbox register for a port-A read or write operation. When the AO-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIF02 output-register data for output.
IRA
Input-Ready Flag
O (Port A)
IRB
Input-Ready Flag
O (Port B)
MBA
Port-A Mailbox Select
I
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONT.)
Symbol MBB Name Port-B Mailbox Select I/O I Description A HIGH level on MBB chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a LOW level selects FIFO1 output-register data for output.
MBF1
Mail1 Register Flag
O
MBF2
Mail2 Register Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is also set HIGH when FIFO2 is reset.
ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is LOW, FIFO2 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is HIGH. ORA is forced LOW when FlFO2 is reset and goes HIGH on the third LOW-to-HIGH transition of CLKA after a word is loaded to empty memory. ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB is LOW, FlFO1 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is HIGH. ORB is forced LOW when FIFO1 is reset and goes HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory. To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FSO and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM. To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FSO and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM. A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The AO-A35 outputs are in the HIGH impedance state when W/RA is HIGH. A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The BO-B35 outputs are in the HIGH impedance state when W/RB is LOW.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1 is reset.
ORA
Output-Ready Flag
O (Port A)
ORB
Output-Ready Flag
O (Port B)
RST1
FIFO1 Reset
I
RST2
FIFO2 Reset
I
W/RA
Port-A Write/ Read Select Port-B Write/ Read Select
I
W/RB
I
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol VCC VI
(2) (2)
Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current (VI < 0 or VI > VCC) Output Clamp Current (VO = < 0 or VO > VCC) Continuous Output Current (VO = 0 to VCC) Continuous Current Through VCC or GND Operating Free Air Temperature Range Storage Temperature Range
Commercial -0.5 to 7 -0.5 to VCC+0.5 -0.5 to VCC+0.5 20 50 50 400 0 to 70 -65 to 150
Unit V V V mA mA mA mA C C
VO
IIK IOK IOUT ICC TA TSTG
NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIH VIL IOH IOL TA Parameter Supply Voltage High-Level Input Voltage Low-Level Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature 0 Min. Max. Unit 4.5 2 0.8 -4 8 70 5.5 V V V mA mA C
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
IDT723622 IDT723632 IDT723642 Commerical tA = 15, 20, 30 ns Parameter VOH VOL ILI ILO ICC ICC
(2)
Test Conditions VCC = 4.5V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, IOH = -4 mA IOL = 8 mA VI = VCC or 0 VO = VCC or 0 VI = VCC -0.2 V or 0 One Input at 3.4 V,
Min. 2.4
Typ.(1)
Max. 0.5 5 5 400
Unit V V A A A mA
Other Inputs at VCC or GND
CSA = VIH CSB = VIH CSA = VIL CSB = VIL
All Other Inputs
A0-A35 B0-B35 A0-A35 B0-35
0 0 1 1 1 4 8
CIN COUT
VI = 0, VO = 0,
f = 1 MHz f = 1 MHZ
pF pF
NOTES: 1. All typical values are at VCC = 5V, TA = 25C. 2. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
723622-15 723632-15 723642-15 Symbol fS tCLK tCLKH tCLKL tDS tENS tRSTS tFSS tDH tENH tRSTH tFSH tSKEW1
(2)
723622-20 723632-20 723642-20 Min. 20 8 8 5 5 6 8.5 1 1 4 3 9 16 Max. 50
723622-30 723632-30 723642-30 Min. 30 10 10 6 6 7 9.5 1 1 5 3 11 20 Max. 33.4 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter Clock Frequency, CLKA or CLKB Clock Cycle Time, CLKA or CLKB Pulse Duration, CLKA or CLKB HIGH Pulse Duration, CLKA and CLKB LOW Setup Time, A0-A35 before CLKA and B0-B35 before CLKB Setup Time, CSA, W/RA, ENA, and MBA before CLKA; CSB, W/RB, ENB, and MBB before CLKB Setup Time, RST1 or RST2 LOW before CLKA or CLKB(1)
Min. 15 6 6 4 4.5 5 7.5 1 1 4 2 7.5 12
Max. 66.7
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH Hold Time, A0-A35 after CLKA and B0-B35 after CLKB Hold Time, CSA, W/RA, ENA, and MBA after CLKA; CSB, W/RB, ENB, and MBB after CLKB Hold Time, RST1 or RST2 LOW after CLKA or CLKB(1)
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH Skew Time, between CLKA and CLKB for ORA, ORB, IRA, and IRB
tSKEW2(2) Skew Time, between CLKA and CLKB for AEA, AEB, AFA, and AFB
NOTES: 1. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 pF
723622L15 723632L15 723642L15 Symbol tA tPIR tPOR tPAE tPAF tPMF Parameter Access Time, CLKA to A0-A35 and CLKB to B0-B35 Propagation Delay Time, CLKA to IRA and CLKB to IRB Propagation Delay Time, CLKA to ORA and CLKB to ORB Propagation Delay Time, CLKA to AEA and CLKB to AEB Propagation Delay Time, CLKA to AFA and and CLKB to AFB Min. 3 2 1 1 1 0 Max. 11 8 8 8 8 8 723622L20 723632L20 723642L20 Min. 3 2 1 1 1 0 Max. 13 10 10 10 10 10 723622L30 723632L30 723642L30 Min. 3 2 1 1 1 0 Max. 15 12 12 12 12 12 Unit ns ns ns ns ns ns
Propagation Delay Time, CLKA to MBF1 LOW or MBF2 HIGH and CLKB to MBF2 LOW or MBF1 HIGH Propagation Delay Time, CLKA to B0-B35(1) and CLKB to A0-A35(2) Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and MBF1 HIGH, and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH
tPMR tMDV tPRF
3 3 1
13.5 11 15
3 3 1
15 13 20
3 3 1
17 15 30
ns ns ns
tEN tDIS
Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB HIGH to B0-B35 Active Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH or W/RB LOW to B0-B35 at HIGH impedance
2 1
12 8
2 1
13 10
2 1
14 11
ns ns
NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTION
RESET The FIFO memories of the IDT723622/723632/723642 are reset separately by taking their reset (RST1, RST2) inputs LOW for at least four port-A clock (CLKA) and four port-B clock (CLKB) LOW-to-HIGH transitions. The reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the input-ready flag (IRA, IRB) LOW, the output-ready flag (ORA, ORB) LOW, the almost-empty flag (AEA, AEB) LOW, and the almost-full flag (AFA, AFB) HIGH. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a FlFO is reset, its input-ready flag is set HIGH after two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory. A LOW-to HIGH transition on a FlFO reset (RST1, RST2) input latches the value of the flag-select (FS0, FS1) inputs for choosing the almost-full and almost-empty offset programming method (see almost-empty and almost-full flag offset programming below). ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAMMING Four registers in the IDT723622/723632/723642 are used to hold the offset values for the almost-empty and almost-full flags. The port-B almost-empty flag (AEB) offset register is labeled X1 and the port-A almost-empty flag (AEA) offset register is labeled X2. The port-A almost-full flag (AFA) offset register is labeled Y1 and the port-B almost-full flag (AFB) offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1 ) . To load a FIFO almost-empty flag and almost-full flag offset registers with one of the three preset values listed in Table1, at least one of the flag-select inputs must be HIGH
during the LOW-to-HIGH transition of its reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be HIGH when FlFO1 reset (RST1) returns HIGH. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 reset (RST2). When using one of the preset values for the flag offsets, the FlFOs can be reset simultaneously or at different times. To program the X1, X2, Y1, and Y2 registers from port A, both FlFOs should be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH transition of the reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723622, IDT723632, or IDT723642, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers ranges from 1 to 252 for the IDT723622; 1 to 508 for the IDT723632; and 1 to 1020 for the IDT723642. After all the offset registers are programmed from port A, the port-B inputready flag (IRB) is set HIGH, and both FIFOs begin normal operation. FIFO WRITE/READ OPERATION The state of the port-A data (A0-A35) outputs is controlled by port-A chip select (CSA) and port-A write/read select (W/ RA). The A0-A35 outputs are in the High-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is LOW, and IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and ORA is HIGH (see Table 2). FIFO reads and writes on port A are independent of any concurrent
FS1 H H H H L L L
FS0 H H L L H H L
RST1
X X X
RST2
X X X
X1 AND Y1 REGlSTERS(1) 64 X 16 X 8 X Programmed from port A
X2 AND Y2 REGlSTERS(2) X 64 X 16 X 8 Programmed from port A
NOTES: 1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA. 2. X2 register holds the offset tor AEA; Y2 register holds the offset for AFB. Table 1. Flag Programming
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IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
port-B operation. The port-B control signals are identical to those of port A with the exception that the port-B write/read select (W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0-B35) outputs is controlled by the portB chip select (CSB) and port-B write/read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW, and IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and ORB is HIGH (see Table 3) . FIFO reads and writes on port B are independent of any concurrent port-A operation. The setup and hold time constraints to the port clocks for the port chip selects and write/read selects are only for enabling write and read operations and are not related to highimpedance control of the data outputs. If a port enable is LOW
during a clock cycle, the port's chip select and write/read select may change states during the setup and hold time window of the cycle. When a FIFO output-ready flag is LOW, the next data word is sent to the FIFO output register automatically by the LOW-to-HIGH transition of the port clock that sets the outputready flag HIGH. When the output-ready flag is HIGH, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port's chip select, write/ read select, enable, and mailbox select. SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIF02.
CSA
H L L L L L L L
W/RA R X H H H L L L L
ENA X L H H L H L H
MBA X X L H L L H H
CLKA X X X X
A0-A35 OUTPUTS In high-impedance state In high-impedance state In high-impedance state In high-impedance state Active, FIFO2 output register Active, FIFO2 output register Active, mail2 register Active, mail2 register
Table 2. Port-A Enable Functlon Table
PORT FUNCTION None None FIFO1 write Mail1 write None FIFO2 read None Mail2 read (set MBF2 HIGH)
CSB
H L L L L L L L
W/RB
X L L L H H H H
ENB X L H H L H L H
MBB X X L H L L H H
CLKB X X X X
B0-B35 OUTPUTS In high-impedance state In high-impedance state In high-impedance state In high-impedance state Active, FIFO1 output register Active, FIFO1 output register Active, mail1 register Active, mail1 register
Table 3. Port-B Enable Function Table
PORT FUNCTION None None FIFO2 write Mail2 write None FIFO1 read None Mail1 read (set MBF1 HIGH)
5.22
11
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
OUTPUT-READY FLAGS (ORA, ORB) The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the output-ready flag is HIGH, new data is present in the FIFO output register. When the output-ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an output-ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the output-ready flag synchronizing clock. Therefore, an output-ready flag is LOW if a word in memory is the next data to be sent to the FlFO output register and three cycles of the port Clock that reads data from the FIFO have not elapsed since the time the word was written. The output-ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock
occurs, simultaneously forcing the output-ready flag HIGH and shifting the word to the FIFO output register. A LOW-to-HIGH transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 7 and 8). INPUT-READY FLAGS (IRA, IRB) The input-ready flag of a FlFO is synchronized to the port clock that writes data to its array. When the input-ready flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the input-ready flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an input-ready flag monitors a write pointer and read pointer comparator that indicates when the FlFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of two cycles of the
IDT723622(1,2) 0 1 to X1 (X1+1) to [256-(Y1+1)] (256-Y1) to 255 256
Number of Words in FIFO IDT723632(1,2) 0 1 to X1 (X1+1) to [512-(Y1+1)] (512-Y1) to 511 512
IDT723642(1,2) 0 1 to X1 (X1+1) to [1024-(Y1+1)] (1024-Y1) to 1023 1024
S ynchronized to CLKB ORB AEB L L H H H H L H H H
Synchronized to CLKA AFA IRA H H H H L L H H H L
Table 4. FIF01 Flag Operatlon Notes: 1. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from port A. 2. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
IDT723622(1,2) 0 1 to X2 (X2+1) to [256-(Y2+1)] (256-Y2) to 255 256
Number of Words in FIFO IDT723632(1,2) 0 1 to X2 (X2+1) to [512-(Y2+1)] (512-Y2) to 511 512
IDT723642(1,2) 0 1 to X2 (X2+1) to [1024-(Y2+1)] (1024-Y2) to 1023 1024
S ynchronized to CLKA ORA AEA L L H H H H L H H H
Synchronized to CLKB AFB IRB H H H H L L H H H L
Table 5. FIF02 Flag Operatlon Notes: 1. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from port A. 2. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
5.22 12
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
input-ready flag synchronizing clock. Therefore, an inputready flag is LOW if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the input-ready flag synchronizing Clock after the read sets the input-ready flag HIGH. A LOW-to-HIGH transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 9 and 10). ALMOST-EMPTY FLAGS (AEA, AEB) The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an almost-empty flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset programming above). An almost empty Flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the almost-empty flag synchronizing clock are required after a FIFO write for its almost-empty flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An almost-empty flag is set HIGH by the second LOWto-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. (See Figures 11 and 12). ALMOST-FULL FLAGS (AFA AFB AFA, AFB) The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an almost-full flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almostfull state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FlFO reset or programmed from port A (see
almost-empty flag and almost-full flag offset programming above). An almost-full flag is LOW when the number of words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1024-Y) for the IDT723622, IDT723632, or IDT723642 respectively. An almost-full flag is HIGH when the number of words in its FIFO is less than or equal to [256-(Y+1)], [512(Y+1)], or [1024-(Y+1)] for the IDT723622, IDT723632, or IDT723642 respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the almost-full flag synchronizing clock are required after a FIFO read for its almostfull flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [256/512/1024-(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [256/512/1024-(Y+1)]. An almost-full flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [256/512/1024-(Y+1)]. A LOW-to-HIGH transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [256/512/1024-(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle (see Figures 13 and 14).
MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes BO-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and with MBB HIGH. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port mailbox select input is LOW and from the mail register when the portmailbox select input is HIGH. The mail1 register flag (MBF1 ) is set HIGH by a LOW-to-HIGH transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB and with MBB HIGH. The mail2 register flag (MBF2) is set HIGH by a LOWto-HIGH transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA and with MBA HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register.
5.22
13
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA tRSTH CLKB tRSTS tFSS tFSH
RST1
FS1,FS0 tPIR IRA tPOR ORB 0,1 tPIR
AEB AFA MBF1
tRSF
tRSF tRSF
3022 drw 04
Figure 1. FIFO1 Reset Loading X1 and Y1 with a Preset Value of NOTE: 1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
Eight(1).
CLKA
4
RST1, RST2
FS1,FS0 IRA ENA 0,0
tFSS tFSH
tPIR tENS tENH tSKEW1(1)
tDS A0 - A35
tDH
AFA Offset
(Y1)
AEB Offset
(X1)
AFB Offset
(Y2)
AEA Offset
(X2)
First Word to FIFO1
CLKB IRB
1
2
tPIR
3022 drw 05
NOTES: 1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tSKEW1, then IRB may transition HIGH one cycle later than shown. 2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles. Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset.
5.22
14
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKA IRA tCLKL
tENS tENS
tENH tENH
CSA
W/RA tENS MBA tENS ENA tDS A0 - A35
NOTE: 1. Written to FIFO1. Figure 3. Port-A Write Cycle Timing for FIFO1
tENH
tENH tDH W1(1)
tENS
tENH
tENS
tENH
W2(1)
No Operation
3022 drw 06
tCLK tCLKH CLKB IRB tCLKL
tENH tENS tENS tENH tENH
CSB W/RB
MBB
tENS tENS tENH tDH W2(1) No Operation
3022 drw 07
tENS
tENH tENS
tENH
ENB B0 - B35
NOTE: 1. Written to FIFO2. Figure 4. Port-B Write Cycle Timing for FIFO2.
tDS W1(1)
5.22
15
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKB ORB tCLKL
CSB W/RB
tENS MBB tENH ENB tMDV B0 - B35
NOTE: 1. Read From FIFO1. Figure 5. Port-B Read Cycle Timing for FIFO1.
tENS
tENH tENS tA
tENH No Operation W3 (1)
3022 drw 08
tA W1(1) W2(1)
tDIS
tEN
tCLK tCLKH CLKA ORA tCLKL
CSA
W/RA tENS tENH ENA tDMV tEN A0 - A35
NOTE: 1. Read From FIFO2. Figure 6. Port-A Read Cycle Timing for FIFO2.
MBA
tENS
tENH tENS tA
tENH No Operation W3(1)
3022 drw 09
tA W1(1) W2(1)
tDIS
5.22
16
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKA tCLKL
CSA
WRA MBA
LOW HIGH tENS tENS tENH tENH
ENA IRA A0 - A35 HIGH tDS W1 tSKEW1 CLKB ORB
(1)
tDH
tCLKH 1
tCLK tCLKL 2 3 tPOR tPOR
Old Data in FIFO1 Output Register LOW HIGH LOW tENS tENH
CSB W/RB
MBB ENB
tA B0 -B35 Old Data in FIFO1 Output Register W1
3022 drw 10
NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB cycle later than shown. Figure 7. ORB Flag Timing and First Data Word Fallthrough when FIFO1 is Empty.
5.22
17
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLKH CLKB
tCLK
tCLKL
CSB W/RB
MBB
LOW LOW tENS tENS tENH tENH
ENB IRB B0 - B35 HIGH tDS W1 tSKEW1 CLKA ORA
(1)
tDH tCLK tCLKL 2 3 tPOR Old Data in FIFO2 Output Register tPOR
tCLKH 1
CSA
W/RA MBA ENA
LOW LOW LOW tENS tENH
tA A0 -A35 Old Data in FIFO2 Output Register W1
3022 drw 11
NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA cycle later than shown. Figure 8. ORA Flag Timing and First Data Word Fallthrough when FIFO2 is Empty.
5.22
18
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKB tCLKL
CSB W/RB
MBB ENB
LOW HIGH LOW tENS tENH
ORB B0 -B35
HIGH tA
Previous Word in FIFO1 Output Register Next Word From FIFO1
(1)
tSKEW1 CLKA IRA FIFO1 Full LOW HIGH
tCLK tCLKH 1 tCLKL 2 tPIR tPIR
CSA
WRA MBA
tENS tENS
tENH tENH tDH
To FIFO1
ENA tDS A0 - A35
3022 drw 12
NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown. Figure 9. IRA Flag Timing and First Available Write when FIFO1 is Full.
5.22
19
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKA tCLKL
CSA
W/RA MBA ENA ORA A0 -A35
LOW LOW LOW tENS tENH
HIGH tA
Previous Word in FIFO2 Output Register Next Word From FIFO2
tSKEW1 (1) tCLKH CLKB IRB
FIFO2 FULL
tCLK tCLKL 2 tPIR tPIR 1
CSB WRB
MBB
LOW LOW tENS tENS tENH tENH tDH
To FIFO2
3022 drw 13
ENB tDS B0 - B35
NOTE: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown. Figure 10. IRB Flag Timing and First Available Write when FIFO2 is Full.
CLKA tENS ENA tSKEW2 CLKB
(1)
tENH
1
2 tPAE tPAE
(X1+1) Words in FIFO1
AEB
ENB
X1 Word in FIFO1
tENS
tENH
3022 drw 14
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. Figure 11. Timing for AEB when FIFO2 is Almost Empty.
5.22
20
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB tENS ENB tSKEW2 CLKA
(1)
tENH
1
2 tPAE tPAE
(X2+1) Words in FIFO2
AEA
ENA
X2 Words in FIFO2
tENS
tENH
3022 drw 15
NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. Figure 12. Timing for AEA when FIFO2 is Almost Empty.
tSKEW2 CLKA tENS ENA tPAF tENH
(1)
1
2
tPAF
(D-Y1) Words in FIFO1
AFA
CLKB
[D-(Y1+1)] Words in FIFO1
tENS ENB
tENH
3022 drw 16
NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO. 3. D = Maximum FIFO Depth = 256 for the 723622, 512 for the 723632, 1024 for the 723642. Figure 13. Timing for AFA when FIFO1 is Almost Full.
5.22
21
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tSKEW2 CLKB tENS ENB tPAF tENH
(1)
1
2
tPAF (D-Y2) Words in FIFO2
AFB
CLKA
[D-(Y2+1)] Words in FIFO2
tENS ENA
tENH
3022 drw 17
NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown. 2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO. 3. D = Maximum FIFO Depth = 256 for the 723622, 512 for the 723632, 1024 for the 723642. Figure 14. Timing for AFB when FIFO2 is Almost Full.
CLKA tENS
tENH
CSA
W/RA MBA ENA A0 - A35 tDS W1 tDH
CLKB
MBF1 CSB W/RB
MBB
tPMF
tPMF
tENS ENB tEN B0 - B35 FIFO1 Output Register tMDV tPMR
tENH
tDIS W1 (Remains valid in Mail1 Register after read)
3022 drw 18
Figure 15. Timing for Mail1 Register and MBF1 Flag.
5.22
22
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB tENS
tENH
CSB W/RB
MBB ENB tDS W1 tDH
B0 - B35
CLKA
MBF2 CSA
W/RA MBA
tPMF
tPMF
tENS ENA tEN A0 - A35 FIFO2 Output Register
Figure 16. Timing for Mail2 Register and MBF2 Flag.
tENH
tMDV
tPMR
tDIS W1 (Remains valid in Mail 2 Register after read)
3022 drw 19
5.22
23
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 300 f data = 1/2 f s TA = 25C 250 C L = 0pF V CC = 5.5 V V CC = 5.0 V
I CC(f) - Supply Current - mA
200
150 V CC = 4.5 V
100
50
0 0 10 20 30 40 50 60 70
3022 drw 18
fs - Clock Frequency - MHz
Figure 17.
CALCULATING POWER DISSIPATION The ICC(f) current for the graph in Figure 17 was taken while simultaneously reading and writing a FIFO on the IDT723622/723632/723642 with CLKA and CLKB set to fs. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of IDT723622/723632/723642 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. With ICC(f) taken from Figure 17, the maximum power dissipation (PT) of the IDT723622/723632/723642 may be calculated by: PT = VCC x [ICC(f) + (N x ICC x dc)] + (CL x VCC2 X fo) where: N = number of inputs driven by TTL levels ICC= increase in power supply current for each input at a TTL HIGH level dc = duty cycle of inputs at a TTL HIGH level of 3.4 V CL = output capacitance load fo = switching frequency of an output When no read or writes are occurring on the IDT723632, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fs is calculated by: PT = VCC x fs x 0.184 mA/MHz
5.22 24
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5V
1.1 k From Output Under Test 680 30 pF
(1)
PROPAGATION DELAY LOAD CIRCUIT 3V Timing Input tS Data, Enable Input 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable tPLZ Low-Level Output 3V 1.5 V 1.5 V tPZL 1.5 V tPZH 1.5 V VOL VOH High-Level Output tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTE: 1. Includes probe and jig capacitance. Figure 18. Load Circuit and Voltage Waveforms.
GND 3V 1.5 V tW 3V 1.5 V GND
1.5 V GND th 3V 1.5 V GND
High-Level Input
Low-Level Input
1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS
1.5 V
GND 3 V
Input
3V 1.5 V tPD 1.5 V GND tPD VOH 1.5 V 1.5 V VOL
OV
In-Phase Output
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
3022 drw 20
5.22
25
IDT723622/723632/723642 CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXXX Device Type X Power XX Speed X Package X Process/ Temperature Range
BLANK PF PQF 15 20 30 L
Commercial (0C to +70C) Thin Quad Flat Pack Plastic Quad Flat Pack Commercial Only Clock Cycle Time (tCLK) Speed in Nanoseconds Low Power
723622 256 x 36 Synchronous BiFIFO 723632 512 x 36 Synchronous BiFIFO 723642 1024 x 36 Synchronous BiFIFO
3022 drw 22
5.22
26

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